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w742e/c811 4-bit microcontroller publication release date: april 15, 2005 - 1 - revision a2 table of contents- 1. general description ......................................................................................................... 3 2. features ....................................................................................................................... .......... 3 3. pin configuration .............................................................................................................. .5 3.1 w742c811 pad list....................................................................................................... 6 4. pin description................................................................................................................ ..... 9 5. functional description.................................................................................................. 11 5.1 program counter (pc).................................................................................................. 11 5.2 stack register (stack) ............................................................................................... 11 5.3 program memory (rom) .............................................................................................. 12 5.3.1 rom page register (rompr).......................................................................................13 5.3.2 rom addressing mode ..................................................................................................13 5.4 data memory (ram)..................................................................................................... 15 5.4.1 architecture ................................................................................................................... .15 5.4.2 ram page register (page) ..........................................................................................15 5.4.3 wr page register (wrp) ..............................................................................................16 5.4.4 data bank register (dbkrh, dbkrl)...........................................................................17 5.4.5 ram addressing mode...................................................................................................18 5.5 accumulator (acc) ....................................................................................................... 19 5.6 arithmetic and logic unit (alu) ................................................................................... 19 5.7 main oscillator .............................................................................................................. 19 5.8 sub-oscillator ................................................................................................................ 2 0 5.9 dividers ....................................................................................................................... .. 20 5.10 dual-clock operation .................................................................................................... 20 5.11 watchdog timer (wdt)................................................................................................ 21 5.12 timer/counter ............................................................................................................... 22 5.12.1 timer 0 (tm0)...............................................................................................................22 5.12.2 timer 1 (tm1)...............................................................................................................23 5.13 mode register 0 (mr0) ................................................................................................ 25 5.13.1 mode register 1 (mr1) ................................................................................................25 5.14 interrupts..................................................................................................................... .. 25 5.15 stop mode operation.................................................................................................... 27 5.15.1 stop mode wake-up enable flag for rc and rd port (sef) ......................................27 5.16 hold mode operation.................................................................................................... 27
w742e/c811 - 2 - 5.16.1 hold mode release enable flag (h ef, hefd)..... .......................... ................... ..........29 5.16.2 interrupt enable flag (ief) ...........................................................................................29 5.16.3 port enable flag (pef, p1ef) .....................................................................................30 5.16.4 hold mode release condition flag (hcf, hcfd) .................... .......................... .........30 5.16.5 event flag (evf,evfd) ...............................................................................................31 5.17 reset function.............................................................................................................. 32 5.18 input/output ports ra, rb & p0................................................................................... 32 5.18.1 port mode 0 register (pm0).........................................................................................33 5.18.2 port mode 1 register (pm1).........................................................................................34 5.18.3 port mode 2 register (pm2).........................................................................................34 5.18.4 port mode 6 register (pm6).........................................................................................34 5.18.5 serial i/o interface .......................................................................................................35 5.19 input ports rc .............................................................................................................. 37 5.19.1 port status register 0 (psr0)......................................................................................39 5.20 input ports rd .............................................................................................................. 39 5.20.1 port status register 1 (psr1)......................................................................................40 5.21 output port re & rf .................................................................................................... 41 5.22 input port p1 ................................................................................................................. 4 1 5.23 dtmf output pin (dtmf) ............................................................................................ 41 5.23.1 dtmf register ..............................................................................................................42 5.23.2 dual tone control register (dtcr).............................................................................42 5.24 mfp output pin (mfp) ................................................................................................. 42 5.25 lcd controller/driver ................................................................................................... 44 5.25.1 lcd ram addressing method ......................................................................................45 5.25.2 lcd voltage and contrast adjusting..............................................................................46 5.25.3 seg32-seg39 using as dc output (nmos open drain type) ......................................47 5.25.4 the output waveforms for the lcd driving mode .........................................................47 6. absolute maximum ratings............................................................................................ 48 7. dc characteristics .......................................................................................................... 48 8. ac characteristics .......................................................................................................... 49 9. instruction set table ..................................................................................................... 50 10. package dimensions ......................................................................................................... 59 11. revision history ............................................................................................................... .60
w742e/c811 publication release date: april 15, 2005 - 3 - revision a2 1. general description the w742e/c811 (w742c811 is mask type, W742E811 is electrical erasable eprom type) is a high- performance 4-bit microcontroller ( c) that built in 640-dot lcd driver. the device contains a 4-bit alu, two 8-bit timers, two dividers in dual-clock operation, a 40 16 lcd driver, ten 4-bit i/o ports (including 2 output port for led driving), multiple frequency output, and one channel dtmf generator. there are also eleven interrupt sources and 16-level stack buffer. the w742e/c811 operates on very low current and has three power reduction modes, hold mode, stop mode and slow mode, which help to minimize power dissipation. 2. features ? operating voltage ? 2.4v ? 5.5v for mask type ? 2.4v ? 4.8v for electrical erasable eprom type ? dual-clock operation ? main oscillator ? 3.58 mhz or 400 khz can be selected by code option ? crystal or rc oscillator can be selected by code option ? sub-oscillator ? connect to 32.768 khz crystal only ? memory ? 16384(16k) x 16 bit program rom (including 64k x 4 bit look-up table) ? 5120(5k) x 4 bit data ram (including 16 nibbles x 16 pages working registers) ? 40 x 16 lcd data ram ? 40 input/output pins ? port for input only: 3 ports/12 pins ? input/output ports: 3 ports/12 pins ? high sink current output port for led driving: 2 port /8 pins ? dc output port: 2 ports/ 8 pins (selected by code option) ? power-down mode ? hold mode: no operation (main oscilla tor and sub-oscillator still operate) ? stop mode: no operation (main oscilla tor and sub-oscillator are stopped) ? slow mode: main oscillator is stopped, system is operated by the sub-oscillator (32.768 khz)
w742e/c811 - 4 - ? eleven interrupt sources ? four internal interrupts (divider0, divider1, timer 0, timer 1) ? seven external interrupts (rc.0-3, p1.2 ( int0 ), serial port, p1.3 ( int1 )) ? lcd driver output ? 40 segments x 16 commons ? 1/8 or 1/16 duty (selected by code option) 1/5 bias driving mode ? clock source should be the sub-oscilla tor clock in the dual-clock operation mode ? 8 level software lcd contrast adjusting ? lcd operating voltage source could come from v dd or vlcd1 pin input ? mfp output pin ? output is software controlled to generate modulating or nonmodulating frequency ? works as frequency output specified by timer 1 ? key tone generator ? dtmf output pin ? output is one channel dual tone multi-frequency signal for dialling ? 8-bit serial i/o interface ? 8-bit transmit/receive mode by internal or external clock source ? two built-in 14-bit frequency dividers ? divider0: the clock source is the main oscillator (fosc) ? divider1: the clock source is the sub-oscillator (fs) ? two built-in 8-bit programmable countdown tmers ? timer 0: one of two internal clock frequencies (f osc /4 or f osc /1024) can be selected ? timer 1: with auto-reload function and one of two internal clock frequencies (f osc or f osc /64 or fs) can be selected (signal output through mfp pin) ? built-in 18/15-bit watchdog timer selectable for system reset, enable/disable by code option ? powerful instruction set ? 16-level stack buffer ? packaged in 100-pin qfp
w742e/c811 publication release date: april 15, 2005 - 5 - revision a2 3. pin configuration w742e/c811 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 18 19 9 7 8 9 0 1 2 3 4 5 6 7 8 9 20 21 22 23 24 0 12 3 33 345 3 33 6 3 78 33 90 4 51 52 53 54 55 56 57 58 59 60 61 62 63 64 065 25 26 27 28 29 30 4 123 45 6 78 9 444444445 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 8 8 8 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 1 0 seg35 seg36 seg37 seg38 com15 seg39 com14 com12 com11 com08 p01 p00 p11 p12 p13 cn seg02 seg08 cp vlcd1 com02 com03 com04 com05 com06 com07 seg00 s e g 1 5 s e g 1 4 s e g 1 3 s e g 1 2 x i n 1 x o u t 1 r c 0 r c 1 r c 3 r d 0 com13 r c 2 s e g 1 8 s e g 1 7 s e g 3 0 com10 com09 com00 s e g 1 6 r d 2 mfp r d 1 ra0 seg07 s e g 1 1 100-pin qfp com01 seg32 seg31 seg33 seg34 ra2 ra3 rb0 rb1 rb2 rb3 xout2 xin2 vss r d 3 r e 0 r e 1 r e 2 r e 3 r f 0 r f 1 r f 2 r f 3 / r e s e t v d d p02 p03 p10 seg01 seg03 seg04 seg05 seg06 seg09 seg10 s e g 1 9 s e g 2 0 s e g 2 1 s e g 2 2 s e g 2 3 s e g 2 4 s e g 2 7 s e g 2 8 s e g 2 9 s e g 2 5 s e g 2 6 ra1 dtmf (k0.0) (k0.1) (k0.2) (k0.3) (k1.0) (k1.1) (k1.2) (k1.3) [data_io] [vpp] [mode]
w742e/c811 - 6 - 3.1 w742c811 pad list ** shrink factor: 1.000000 ** window: (xl = -1635.00, yl = -2140.00), (xh = 1635.00, yh = 2140.00) ** windows size: width = 3270.00, length = 4280.00 ============================================================================= pad no pad name pin name x y ============================================================================= 1 seg<31> 1 -1530.00 1970.48 2 seg<32> 2 -1530.00 1840.48 3 seg<33> 3 -1530.00 1710.48 4 seg<34> 4 -1530.00 1580.48 5 seg<35> 5 -1530.00 1450.48 6 seg<36> 6 -1530.00 1320.48 7 seg<37> 7 -1530.00 1190.48 8 seg<38> 8 -1530.00 1060.48 9 seg<39> 9 -1530.00 930.48 10 com<8> 10 -1530.00 800.48 11 com<9> 11 -1530.00 670.48 12 com<10> 12 -1530.00 540.48 13 com<11> 13 -1530.00 410.48 14 com<12> 14 -1530.00 280.48 15 com<13> 15 -1530.00 150.48 16 com<14> 16 -1530.00 20.48 17 com<15> 17 -1530.00 -109.53 18 ra0 18 -1530.00 -233.53 19 ra1 19 -1530.00 -357.53 20 ra2 20 -1530.00 -481.53 21 ra3 21 -1530.00 -605.53 22 rb0 22 -1530.00 -729.53 23 rb1 23 -1530.00 -853.53 24 rb2 24 -1530.00 -977.53 25 rb3 25 -1530.00 -1101.53 26 mfp 26 -1530.00 -1225.53 27 dtmf 27 -1530.00 -1349.53 28 xout2 28 -1530.00 -1473.53 =============================================================================
w742e/c811 publication release date: april 15, 2005 - 7 - revision a2 w742c811 pad list, continued ============================================================================= pad no pad name pin name x y ============================================================================= 29 xin2 29 -1530.00 -1603.53 30 v ss 30 -1530.00 -1733.53 31 xin1 31 -1227.75 -2035.00 32 xout1 32 -1097.75 -2035.00 33 rc0 33 -967.75 -2035.00 34 rc1 34 -837.75 -2035.00 35 rc2 35 -707.75 -2035.00 36 rc3 36 -577.75 -2035.00 37 rd0 37 -447.75 -2035.00 38 rd1 38 -317.75 -2035.00 39 rd2 39 -187.75 -2035.00 40 rd3 40 -57.75 -2035.00 41 re0 41 72.25 -2035.00 42 re1 42 202.25 -2035.00 43 re2 43 332.25 -2035.00 44 re3 44 462.25 -2035.00 45 rf0 45 592.25 -2035.00 46 rf1 46 722.25 -2035.00 47 rf2 47 852.25 -2035.00 48 rf3 48 982.25 -2035.00 49 res 49 1112.25 -2035.00 50 v dd 50 1242.25 -2035.00 51 p00 51 1527.33 -1733.53 52 p01 52 1527.33 -1603.53 53 p02 53 1527.33 -1473.53 54 p03 54 1527.33 -1349.53 55 p10 55 1527.33 -1225.53 56 p11 56 1527.33 -1101.53 57 p12 57 1527.33 -977.53 58 p13 58 1527.33 -853.53 59 cn 59 1527.33 -729.53 =============================================================================
w742e/c811 - 8 - w742c811 pad list, continued ============================================================================= pad no pad name pin name x y ============================================================================= 60 cp 60 1527.33 -605.53 61 vlcd1 61 1527.33 -481.53 62 com<7> 62 1527.33 -354.53 63 com<6> 63 1527.33 -224.53 64 com<5> 64 1527.33 -94.53 65 com<4> 65 1527.33 35.48 66 com<3> 66 1527.33 165.48 67 com<2> 67 1527.33 295.48 68 com<1> 68 1527.33 425.48 69 com<0> 69 1527.33 555.48 70 seg<0> 70 1527.33 685.48 71 seg<1> 71 1527.33 815.48 72 seg<2> 72 1527.33 945.48 73 seg<3> 73 1527.33 1075.48 74 seg<4> 74 1527.33 1205.48 75 seg<5> 75 1527.33 1335.48 76 seg<6> 76 1527.33 1465.48 77 seg<7> 77 1527.33 1595.48 78 seg<8> 78 1527.33 1725.48 79 seg<9> 79 1527.33 1855.48 80 seg<10> 80 1527.33 1985.48 81 seg<11> 81 1242.25 2019.15 82 seg<12> 82 1112.25 2019.15 83 seg<13> 83 982.25 2019.15 84 seg<14> 84 852.25 2019.15 85 seg<15> 85 722.25 2019.15 86 seg<16> 86 592.25 2019.15 87 seg<17> 87 462.25 2019.15 88 seg<18> 88 332.25 2019.15 89 seg<19> 89 202.25 2019.15 90 seg<20> 90 72.25 2019.15 =============================================================================
w742e/c811 publication release date: april 15, 2005 - 9 - revision a2 w742c811 pad list, continued ============================================================================= pad no pad name pin name x y ============================================================================= 91 seg<21> 91 -57.75 2019.15 92 seg<22> 92 -187.75 2019.15 93 seg<23> 93 -317.75 2019.15 94 seg<24> 94 -447.75 2019.15 95 seg<25> 95 -577.75 2019.15 96 seg<26> 96 -707.75 2019.15 97 seg<27> 97 -837.75 2019.15 98 seg<28> 98 -967.75 2019.15 99 seg<29> 99 -1097.75 2019.15 100 seg<30> 100 -1227.75 2019.15 ============================================================================= 4. pin description symbol i/o function xin2 i input pin for sub-oscillator. connected to 32.768 khz crystal only. xout2 o output pin for sub-oscillator wi th internal oscillation capacitor. connected to 32.768 khz crystal only. xin1 i input pin for main-oscillator. connected to 3.58 mhz crystal or re sistor to generate system clock. xout1 o output pin for main-oscillator. connected to 3.58 mhz crystal or re sistor to generate system clock. ra0-ra3 data_io i/o input/output port. input/output mode specified by port mode 1 register (pm1). ra.3: serial data input/output for electrical erasable eprom type rb0 ? rb3 i/o input/output port. input/output mode specified by port mode 2 register (pm2). rc0 ? rc3 i input port only. each pin has an independe nt interrupt capability. rd0 ? rd3 i input port only. this port can release hold mode but can not occur interrupt service routine.
w742e/c811 - 10 - pin description, continued symbol i/o function re0 ? re3 rf0 ? rf3 o output port only. cmos type wi th high sink current capacity for the led application. p00 ? p03 i/o input/output port. input/output mode specified by port mode 6 register (pm6). p0.0 and p0.1 can be a serial i/o interface selected by sir register. p0.0 indicates serial clock, p0.1indicates serial data. p10 ? p13 mode i input port only. p1.2 & p1.3 indicates hardware interrupt(/int0 & /int1) p1.3: mode select for electrical erasable eprom type mfp o output pin only, default in low state. this pin can output modulating or nonmodulating frequency, or timer 1 clock output specified by mode register 1 (mr1). dtmf o this pin can output dual-ton e multifrequency signal for dialling. res v pp i system reset pin with internal pull-high resistor. v pp : supply programming voltage, without internal pull-high resistor for electrical erasable eprom type for avoiding high voltage programming damage seg0 ? seg31 o lcd segment output pins. com0 ? com15 o lcd common signal output pins. the lcd alternating frequency can be selected by code option. seg32 ? seg39 (k00 ? k03, k10 ? k13) o lcd segment output pins or dc n-mos open drain output pins selected by code option. cp, cn i connection terminals for lcd voltage double capacitor (0.1 f), tuning the capacitor value can reduce the lcd driving current. vlcd1 i lcd supply voltage input or connect capacitor (0.1 f) to ground when enable internal pump lcd voltage v dd i positive power supply (+). v ss i negative power supply (-).
w742e/c811 publication release date: april 15, 2005 - 11 - revision a2 5. functional description 5.1 program counter (pc) organized as an 14-bit binary counter (pc0 to pc13), the program counter generates the addresses of the 16384(16k) 16 on-chip rom containing the program instruction words. when the interrupt or initial reset conditions are to be executed, the corresponding address will be loaded into the program counter directly. from address 0000h to 0023h are reserved for reset and interrupt service routine. the format used is shown below. table 1 vector address and interrupt priority item address interrupt priority initial reset 0000h - int 0 (divider0) 0004h 1st int 1 (timer 0) 0008h 2nd int 2 (port rc) 000ch 3rd int 3 (port 1.2(/int0)) 0010h 4th int 4 (divider1) 0014h 5th int 5 (serial i/o) 0018h 6th int 6 (port1.3(/int1)) 001ch 7th int 7 (timer 1) 0020h 8th code start 0024h - 5.2 stack register (stack) the stack register is organized as 51 bits x 16 levels (first-in, last-out). when either a call subroutine or an interrupt is executed, the program counter (pc), tab0, tab1, tab2, tab3, dbkrl, dbkrh, wrp, rompr, page, acc and cf will be pushed into the stack register automatically. at the end of a call subroutine or an interrupt service subroutine, the rtn (only restore the program counter) and rtn #i instruction could pop the contents of the stack register into the corresponding registers. it can restore part of contents of stack buffer. when the stack register is pushed over the 16th level, the contents of the first level will be overwritten. in th e other words, the stack register is always 16 levels deep. the bit definition of #i is listed below. i = 0000 0000 pop pc from stack only bit0 = 1 pop tab0, tab1, tab2, tab3 from stack bit1 = 1 pop dbkrl, dbkrh from stack bit2 = 1 pop wrp from stack bit3 = 1 pop rompr from stack bit4 = 1 pop page from stack bit5 = 1 pop acc from stack bit6 = 1 pop cf from stack
w742e/c811 - 12 - 5.3 program memory (rom) the read-only memory (rom) is used to store program codes or the look-up table code that can arranged up to 65536 (64k) 4 bits. the program rom is divided into eight pages; the size of each page is 2048(2k) 16 bits. so the total rom size is 16384(16k) 16 bits. before the jump or subroutine call instructions are to be executed, the destination rom page register (rompr) must be determined firstly. the rom page can be selected by executing the mov rompr,#i or mov rompr,ram instructions. but the branch decision instructions (e.g. jb0, skb0, jz, jc, ...) must jump into the same rom page. each look-up table element is composed of 4 bits, so the look-up table can be addressed up to 65536(64k) elements. it uses instructions mov tab0,r mov tab1,r mov tab2,r mov tab3,r to determine the look-up table element address. the look-up table address is 4 times pc counter. instruction movc r is used to read the look-up table content and save data into the ram. the organization of the program memory is shown in figure 5-1. 0000 h 16 bits 16384 * 16 bits 0fffh 0800h : : each element (4 bits) of the look-up table : 07ffh : 1000h 1fffh 1800h : : : 17ffh : 2000h 2fffh 2800h : : : 27ffh : 3800h : : 37ffh : 3000h 3fffh : all program memory can be used to store instruction code or look-up table page 0 page 1 page 2 page 3 page 4 page 5 page 6 page 7 figure 5-1 program memory organization
w742e/c811 publication release date: april 15, 2005 - 13 - revision a2 5.3.1 rom page register (rompr) the rom page register is organized as a 4-bit binary register. the bit descriptions are as follows: ww 0 1 2 3 rompr w note: w means write only. bit 3 is reserved. bit 2, bit 1, bit 0 rom page bits: 000 = rom page 0 (0000h - 07ffh) 001 = rom page 1 (0800h - 0fffh) 010 = rom page 2 (1000h - 17ffh) 011 = rom page 3 (1800h - 1fffh) 100 = rom page 4 (2000h - 27ffh) 101 = rom page 5 (2800h - 2fffh) 110 = rom page 6 (3000h - 37ffh) 111 = rom page 7 (3800h - 3fffh) 5.3.2 rom addressing mode 1. direct addressing bit 13-0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 pc 2. far jump or call bit 13-0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p2 p1 p0 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 pc p0-2 is rom page register(rompr) example: mov rompr,#i jmp label_a or mov rompr,#i call sub_a
w742e/c811 - 14 - 3. conditional jmp bit 13-0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 pc jmp into the same page example: jb0 lable_a0 jb1 lable_a1 jb2 lable_a2 jb3 lable_a3 jz label_az jnz label_anz jc label_ac jnc label_anc 4. look-up table bit 15-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ta33 ta32 ta31 ta30 ta23 ta22 ta21 ta20 ta13 ta12 ta11 ta10 ta03 ta02 ta01 ta00 pc*4 look-up table address = pc address*4 example: org tab_addr ; real_tab_addr = tab_addr*4 table 00h, 01h, 02h, 0ah, 0ch, 0dh, 0eh, 0fh endt mov tab0, real_tab_addr_b0_3 ;set look-up table address mov tab1, real_tab_addr_b4_7 mov tab2, real_tab_addr_b8_11 mov tab3, real_tab_addr_b12_15 movc ram ;get look-up table value to ram
w742e/c811 publication release date: april 15, 2005 - 15 - revision a2 5.4 data memory (ram) 5.4.1 architecture the static data memory (ram) used to store data is arranged up to 5120(5k) 4 bits. the data ram is divided into 40 banks; each bank has 128 4 bits. executing the mov dbkrl,wr,mov dbkrh,wr or mov dbkrl,#i, mov dbkrh,#i instructions can determine which data bank is used. the data memory can be accessed directly or indirectly and the data bank register has to be confirmed firstly. in the indirect addressing mode, each data bank will be divided into eight pages. the ram page register has to be setting when in the indirect accessing ram. the instructions mov wrn,@wrq mov @wrq,wrn could read or write the whole memory in the indirect addressing mode. the ram address of @wrq indicates to (dbkrh)*800h + (dbkrl)*80h + (ram page)*10h + (wrq). the organization of the data memory is shown in figure 5-2. data bank 00 5120 address 0000h 4 bits 5120 * 4 bits : 007fh 0080h : 00ffh data bank 01 : : : 1380h : 13ffh data bank 39 (or working registers bank) 00h : 0fh 10h : 1fh 20h : 2fh 70h : 7fh : : 1st data ram page (or 1st wr page) 2nd data ram page (or 2nd wr page) 8th data ram page (or 8th wr page) 3rd data ram page (or 3rd wr page) (or working registers bank) figure 5-2 data memory organization the 1st and 2nd data bank (00h to 7fh & 80h to 0ffh) in the data memory can also be used as the working registers (wr). it is also divided into sixteen pages. each page contains 16 working registers. when one page is used as working register, the others can be used as the normal data memory. the wr page register can be switched by executing the mov wrp,r or mov wrp,#i instructions. the data memory can not do the logical operation directly with the immediate data, it has to via the working register. 5.4.2 ram page register (page) the page register is organized as a 4-bit binary register. the bit descriptions are as follows: r/w r/w r/w 0 1 2 3 page note: r/w means read/write available. bit 3 is reserved. bit 2, bit 1, bit 0 ram page bits:
w742e/c811 - 16 - 000 = page 0 (00h - 0fh) 001 = page 1 (10h - 1fh) 010 = page 2 (20h - 2fh) 011 = page 3 (30h - 3fh) 100 = page 4 (40h - 4fh) 101 = page 5 (50h - 5fh) 110 = page 6 (60h - 6fh) 111 = page 7 (70h - 7fh) 5.4.3 wr page register (wrp) the wr page register is organized as a 4-bit binary register. the bit descriptions are as follows: r/w r/w r/w 0 1 2 3 wrp r/w note: r/w means read/write available. bit 3, bit 2, bit 1, bit 0 working registers page bits: 0000 = wr page 0 (00h - 0fh) 0001 = wr page 1 (10h - 1fh) 0010 = wr page 2 (20h - 2fh) 0011 = wr page 3 (30h - 3fh) 0100 = wr page 4 (40h - 4fh) 0101 = wr page 5 (50h - 5fh) 0110 = wr page 6 (60h - 6fh) 0111 = wr page 7 (70h - 7fh) 1000 = wr page 8 (80h - 8fh) 1001 = wr page 9 (90h - 9fh) 1010 = wr page a (a0h - afh) 1011 = wr page b (b0h - bfh) 1100 = wr page c (c0h - cfh) 1101 = wr page d (d0h - dfh) 1110 = wr page e (e0h - efh) 1111 = wr page f (f0h - ffh)
w742e/c811 publication release date: april 15, 2005 - 17 - revision a2 5.4.4 data bank register (dbkrh, dbkrl) the data bank register is organized as two 4-bit binary register. the bit descriptions are as follows: r/w r/w r/w 0 1 2 3 dbkrl r/w r/w 0 1 2 3 dbkrh r/w note: r/w means read/write available. bit5, bit 4, bit3, bit 2, bit 1, bit 0 data memory bank bits: 000000 = data bank 0 (000h - 07fh) 000001 = data bank 1 (080h - 0ffh) 000010 = data bank 2 (100h - 17fh) 000011 = data bank 3 (180h - 1ffh) 000100 = data bank 4 (200h - 27fh) 000101 = data bank 5 (280h - 2ffh) 000110 = data bank 6 (300h - 37fh) 000111 = data bank 7 (380h - 3ffh) 001000 = data bank 8 (400h - 47fh) 001001 = data bank 9 (480h - 4ffh) 001010 = data bank 10 (500h - 57fh) 001011 = data bank 11 (580h - 5ffh) 001100 = data bank 12 (600h - 67fh) 001101 = data bank 13 (680h - 6ffh) 001110 = data bank 14 (700h - 77fh) 001111 = data bank 15 (780h - 7ffh) 010000 = data bank 16 (800h - 87fh) 010001 = data bank 17 (880h - 8ffh) 010010 = data bank 18 (900h - 97fh) 010011 = data bank 19 (980h - 9ffh) 010100 = data bank 20 (0a00h - 0a7fh) 010101 = data bank 21 (0a80h - 0affh) 010110 = data bank 22 (0b00h - 0b7fh) 010111 = data bank 23 (0b80h - 0bffh) 011000 = data bank 24 (0c00h - 0c7fh) 011001 = data bank 25 (0c80h - 0cffh) 011010 = data bank 26 (0d00h - 0d7fh)
w742e/c811 - 18 - 011011 = data bank 27 (0d80h - 0dffh) 011100 = data bank 28 (0e00h - 0e7fh) 011101 = data bank 29 (0e80h - 0effh) 011110 = data bank 30 (0f00h - 0f7fh) 011111 = data bank 31 (0f80h - 0fffh) 100000 = data bank 32 (1000h - 107fh) 100001 = data bank 33 (1080h - 10ffh) 100010 = data bank 34 (1100h - 117fh) 100011 = data bank 35 (1180h - 11ffh) 100100 = data bank 36 (1200h - 127fh) 100101 = data bank 37 (1280h - 12ffh) 100110 = data bank 38 (1300h - 137fh) 100111 = data bank 39 (1380h - 13ffh) 5.4.5 ram addressing mode 1. direct addressing bit 12-0 12 11 10 9 8 7 6 5 4 3 2 1 0 bh1 bh0 bl3 bl2 bl1 bl0 ra6 ra5 ra4 ra3 ra2 ra1 ra0 ram addr ra0-6 is ram address ; bl0-3 is dbkrl register ; bh0-1 is dbkrh register example: mov dbkrl,#bl_value ; set ram bank mov dbkrh,#bh_value mov a,ram ; get ram data to acc 2. working register addressing bit 7-0 7 6 5 4 3 2 1 0 wp3 wp2 wp1 wp0 wa3 wa2 wa1 wa0 ram addr wa0-3 is working register address ; wp0-3 is wr page register(wrp) example: mov dbkrl,#bl_value ; set ram bank mov dbkrh,#bh_value mov wrp,#i ; set wr page register mova wrn,ram ; mov ram data to working register and acc
w742e/c811 publication release date: april 15, 2005 - 19 - revision a2 3. indirect addressing bit 12-0 12 11 10 9 8 7 6 5 4 3 2 1 0 bh1 bh0 bl3 bl2 bl1 bl0 dp2 dp1 dp0 (wa3 wa2 wa1 wa0) ram addr (wa0-3) is working register contents ; dp0-3 is ram page register(page) bl0-3 is dbkrl register ; bh0-1 is dbkrh register example: mov dbkrl,bl_value ; set ram bank mov dbkrh,bh_value mov page,#ip ; set ram page address,(0-07h) mov wrq,#in ; set wr pointer address;(0-0fh) mov wrn,@wrq ; get the contents of wrq pointing addr to wrn 5.5 accumulator (acc) the accumulator (acc) is a 4-bit register used to hold results from the alu and transfer data between the memory, i/o ports, and registers. 5.6 arithmetic and logic unit (alu) this is a circuit which performs arithmetic and logic operations. the alu provides the following functions: ? logic operations: anl, xrl, orl ? branch decisions: jb0, jb1, jb2, jb3, jnz, jz, jc, jnc, dskz, dsknz, skb0, skb1, skb2, skb3 ? shift operations: shrc, rrc, shlc, rlc ? binary additions/subtractions: adc, sbc, add, sub, adu, dec, inc after any of the above instructions is executed, the status of the carry flag (cf) and zero flag (zf) is stored in the internal registers. cf can be read out by executing mov r, cf. 5.7 main oscillator the w742e/c811 provides a crystal oscillation circui t to generate the system clock through external connections. the 3.58 mhz or 400 khz crystal must be connected to xin1 and xout1, and a capacitor must be connected to xin1 and v ss if an accurate frequency is needed. xin1 xout1 crystal 3.58mhz figure 5-3 system clock oscillator configuration
w742e/c811 - 20 - 5.8 sub-oscillator the sub-oscillator is used in dual-clock operation mode. in the sub-oscillator application, just only the 32768 hz crystal could be connected to xin2 and xout2. 5.9 dividers divider 0 is organized with a 14-bit binary up-counter that is designed to generate periodic interrupt. when the main clock starts action, the divider0 is incremented by each clock (f osc ). the main clock can come from main oscillator or sub-oscillator by setting scr register. when an overflow occurs, the divider0 event flag is set to 1 (evf.0 = 1). then, if the divider0 interrupt enable flag has been set (ief.0 = 1), the interrupt is executed, while if the hold release enable flag has been set (hef.0 = 1), the hold state is terminated. and the last 4-stage of the divider0 can be reset by executing clr divr0 instruction. if the main clock is connected to the 32.768k hz crystal, the evf.0 will be set to 1 periodically at the period of 500 ms. divider 1 is orginized with 13/12 bits up-counter that only has sub-oscillator clock source. if the sub- oscillator starts action, the divider1 is incremented by each clock (fs). when an overflow occurs, the divider1 event flag is set to 1 (evf.4 = 1). then, if the divider1 interrupt enable flag has been set (ief.4 = 1), the interrupt is executed, while if the hold release enable flag has been set (hef.4 = 1), the hold state is terminated. and the last 4-stage of the divider1 can be reset by executing clr divr1 instruction. there are two period time (125 ms & 250 ms) that can be selected by setting the scr.3 bit. when scr.3 = 0 (default), the 250 ms period time is selected; scr.3 = 1, the 125 ms period time is selected. 5.10 dual-clock operation in this dual-clock mode, the normal operation is performed by generating the system clock from the main-oscillator clock (fm). as required, the slow operation can be performed by generating the system clock from the sub-oscillator clock (fs). the exchange of the normal operation and the slow operation is performed by setting the bit 0 of the system clock control register (scr). if the scr.0 is set to 0, the clock source of the system clock generator is main-oscillator clock; if the scr.0 is set to 1, the clock source of the system clock generator is sub-oscillator clock. in the dual-clock mode, the main- oscillator can stop oscillating when the scr.1 is set to 1. when the main clock switch, we must care the following cases: 1. x000b x011b (f osc = fm f osc = fs): we should not exchange the f osc from fm into fs and disable fm simultaneously. we could first exchange the f osc from fm into fs, then disable the main-oscillator. so it should be x000b x001b x011b . 2. x011b x000b (f osc = fs f osc = fm): we should not enable fm and exchange the f osc from fs into fm simultaneously. we could first enable the main-oscillator; the 2nd step is calling a delay subroutine to wait the main-oscillator oscillating stabely; then exchange the f osc from fs into fm is the last step. so it should be x011b x001b delay the fm oscillating stable time x000b . we must remember that the x010b state is inhibitive, because it will induce the system shutdown. the organization of the dual-clock operation mode is shown in figure 5-4.
w742e/c811 publication release date: april 15, 2005 - 21 - revision a2 system clock generator t1 t2 t3 t4 main oscillator xin1 xout1 sub-oscillator xin2 xout2 fosc divider 0 scr : system clock control register ( default = 00h ) bit0 bit1 bit2 bit3 0 : fosc = fm 1 : fosc = fs 0 : fm enable 1 : fm disable 0 : wdt input clock is fosc/2048 1 : wdt input clock is fosc/16384 fm fs enable/disable scr.1 stop hold scr.0 lcd frequency selector f lcd divider 1 int4 hcf.4 scr.3(13/12 bit) 1 : 12 bit 0 : 13 bit daul clock operation mode : - scr.0=0, fosc=fm : scr.0=1, fosc=fs - flcd=fs, in stop mode lcd is turned off. figure 5-4 organization of the dual-clock operation mode 5.11 watchdog timer (wdt) the watchdog timer (wdt) is organized as a 4-bit up counter designed to prevent the program from unknown errors. the wdt can be enabled by mask option code. if the wdt overflows, the chip will be reset. at initial reset, the input clock of the wdt is f osc /1024. the input clock of the wdt can be switched to f osc /16384 by setting scr.2 register. the contents of the wdt can be reset by the instruction clr wdt. in normal operation, the application program must reset wdt before it overflows. a wdt overflow indicates that operation is not under control and the chip will be reset. the wdt overflow period is about 1 s when the system clock (f osc ) is 32 khz and wdt clock input is f osc /2048. the organization of the divider0 and watchdog timer is shown in figure 5-5. the minimum wdt time interval is 1/(f osc /16384 x 16) - 1/(f osc /16384).
w742e/c811 - 22 - q1 q2 q9 q10 q11 q12 q14 q13 fosc s r q hef.0 ief.0 1. reset 2. clr evf,#01h evf.0 hold mode release (hcf.0) divider interrupt ... overflow signal wdt enable disable scr.2 fosc/2048 fosc/16384 option code is reset to "0" qw1 qw2 qw4 qw3 rrrr divider0 system reset 1. reset 2. clr wdt 3. clr divr0 option code is set to "1" figure 5-5 organization of divider0 and watchdog timer 5.12 timer/counter 5.12.1 timer 0 (tm0) timer 0 (tm0) is a programmable 8-bit binary down-counter. the specified value can be loaded into tm0 by executing the mov tm0l(tm0h),r instructions. when the mov tm0l(tm0h),r instructions are executed, it will stop the tm0 down-counting (if the tm0 is down-counting) and reset the mr0.3 to 0, and the specified value can be loaded into tm0. then we can set mr0.3 to 1, that will cause the event flag 1 (evf.1) is reset and the tm0 starts to down count. when it decrements to ffh, timer 0 stops operating and generates an underflow (evf.1 = 1). then, if the timer 0 interrupt enable flag has been set (ief.1 = 1), the interrupt is executed, while if the hold release enable flag 1 has been set (hef.1 = 1), the hold state is terminated. the timer 0 clock input can be set as f osc /1024 or f osc /4 by setting mr0 bit 0. the default timer value is f osc /4. the organization of timer 0 is shown in figure 5-6. if the timer 0 clock input is f osc /4: desired timer 0 interval = (preset value +1) 4 1/f osc if the timer 0 clock input is f osc /1024: desired timer 0 interval = (preset value +1) 1024 1/f osc preset value: decimal number of timer 0 preset value f osc : clock oscillation frequency
w742e/c811 publication release date: april 15, 2005 - 23 - revision a2 fosc/4 fosc/1024 enable disable 1. reset 2. clr evf,#02h 8-bit binary down counter s r q hef.1 ief.1 hold mode release (hcf.1) timer 0 interrupt (int1) 1. reset 2. clr evf,#02h evf.1 mr0.0 (timer 0) set mr0.3 to 1 3. reset mr0.3 to 0 3.set mr0.3 to 1 4 4 mov tm0h,r mov tm0l,r 4.mov tm0l,r or mov tm0h,r figure 5-6 organization of timer 0 5.12.2 timer 1 (tm1) timer 1 (tm1) is also a programmable 8-bit binary down counter, as shown in figure 5-7. timer 1 can output an arbitrary frequency to the mfp pin. the input clock of timer 1 can be one of three sources: f osc /64, f osc or f s . the source can be selected by setting bit 0 and bit 1 of mode register 1 (mr1). at initial reset, the timer 1 clock input is f osc. when the mov tm1l, r or mov tm1h,r instruction is executed, the specified data are loaded into the auto-reload buffer and the tm1 down-counting will be disabled that is mr1.3 is reset to 0 at the same time. if the bit 3 of mr1 is set (mr1.3 = 1), the content of the auto-reload buffer will be loaded into the tm1 down counter, and timer 1 starts to down count, and the event flag 7 is reset (evf.7=0). when the timer decrements to 0ffh, it will generate an underflow (evf.7 = 1) and be auto-reloaded with the specified data, after which it will continue to count down. then, if interrupt enable flag 7 has been set to 1 (ief.7 = 1), an interrupt is executed; if hold mode release enable flag 7 is set to 1 (hef.7 = 1), the hold state is terminated. the specified frequency of timer 1 can be delivered to the mfp output pin by programming bit 2 of mr1. bit 3 of mr1 can be used to make timer 1 stop or start counting. in a case where timer 1 clock input is f t : desired timer 1 interval = (preset value +1) / f t desired frequency for mfp output pin = f t (preset value + 1) 2 (hz) preset value: decimal number of timer 1 preset value f osc : clock oscillation frequency
w742e/c811 - 24 - auto-reload buffer 8 bits mr1.3 underflow signal evf.7 m mfp signal mr1.2 out p 8-bit binary down counter 2 circuit reset reset disable enable fosc/64 fosc mr1.0 (timer 1) s r q 1. reset 2. int7 accept 3. clr evf, #8 0 t f mov tm1l,r or mov tm1h,r 4. set mr1.3 to 1 4 4 mov tm1h,r mov tm1l,r set mr1.3 to 1 mr1.1 fs figure 5-7 organization of timer 1 for example, when f t equals 32768 hz, depending on the preset value of tm1, the mfp pin will output a single tone signal in the tone frequency range from 64 hz to 16384 hz. the relation between the tone frequency and the preset value of tm1 is shown in the table below. table 2 the relation between the tone frequency and the preset value of tm1 c c # b g f e d a # # d # # g f a e n o t tm1 preset value & mfp frequency 3rd octave 4th octave 5th octave 261.63 277.18 293.66 311.13 329.63 349.23 369.99 392.00 415.30 440.00 466.16 493.88 523.25 554.37 587.33 622.25 659.26 698.46 739.99 783.99 830.61 880.00 932.23 987.77 260.06 277.69 292.57 309.13 327.68 372.36 390.09 420.10 443.81 442.81 3eh 3ah 37h 34h 31h 2eh 2bh 29h 26h 22h 24h 20h 468.11 496.48 1eh 1ch 1bh 19h 18h 16h 15h 14h 13h 12h 11h 10h 528.51 564.96 585.14 630.15 655.36 712.34 744.72 780.19 819.20 862.84 910.22 963.76 130.81 138.59 146.83 155.56 164.81 174.61 185.00 196.00 207.65 220.00 233.08 246.94 7ch 75h 6fh 68h 62h 5dh 58h 53h 4eh 45h 49h 41h 131.07 138.84 146.28 156.03 165.49 174.30 184.09 195.04 207.39 221.40 234.05 248.24 tone frequency tone frequency tm1 preset value & mfp frequency tone frequency tm1 preset value & mfp frequency note: central tone is a4 (440 hz).
w742e/c811 publication release date: april 15, 2005 - 25 - revision a2 5.13 mode register 0 (mr0) mode register 0 is organized as a 4-bit binary register (mr0.0 to mr0.3). mr0 can be used to control the operation of timer 0. the bit descriptions are as follows: w w 0 1 2 3 mr0 note: w means write only. bit 0 = 0 the fundamental frequency of timer 0 is f osc /4. = 1 the fundamental frequency of timer 0 is f osc /1024. bit 1 & bit 2 are reserved bit 3 = 0 timer 0 stops down-counting. = 1 timer 0 starts down-counting. 5.13.1 mode register 1 (mr1) mode register 1 is organized as a 4-bit binary register (mr1.0 to mr1.3). mr1 can be used to control the operation of timer 1. the bit descriptions are as follows: w www 0 1 2 3 mr1 note: w means write only. bit 0 = 0 the internal fundamental frequency of timer 1 is f osc . = 1 the internal fundamental frequency of timer 1 is f osc /64. bit 1 = 0 the fundamental frequency source of timer1 is the internal clock. = 0 the fundamental frequency source of timer1 is the sub-oscillator frequency fs (32.768 khz). bit 2 = 0 the specified waveform of the mfp generator is delivered at the mfp output pin. = 1 the specified frequency of timer 1 is delivered at the mfp output pin. bit 3 = 0 timer 1 stops down-counting. = 1 timer 1 starts down-counting. 5.14 interrupts the w742e/c811 provides four internal interrupt sources (divider 0, divider 1, timer 0, timer 1) and seven external interrupt source (port p1.2(/int 0), rc.0-3, serial port, p1.3(/int1)). vector addresses for each of the interrupts are located in the range of program memory (rom) addresses 004h to 023h. the flags ief, pef, and evf are used to control the interrupts. when evf is set to "1" by hardware and the corresponding bits of ief and pef have been set by software, an interrupt is generated. when an interrupt occurs, the corresponding bit of evf will be clear, and all of the interrupts will be inhibited until the en int or mov ief,#i instruction is invoked . normally, the en int instruction will be asserted before the rtn instruction . the interrupts can also be
w742e/c811 - 26 - disabled by executing the dis int instruction. when an interrupt is generated in the hold mode, the hold mode will be released momentarily and interrupt service routine will be executed. after executing interrupt service routine, the c will enter hold mode automatically. the operation flow chart is shown in figure 5-9. the control diagram is shown figure 5-8. s r q s r q s r q ief.0 ief.1 interrupt process circuit interrupt vector generator 004h 008h 020h ief.2 initial reset clr evf,#i instruction dis int instruction initial reset mov ief,#i enable en int evf.1 evf.0 evf.2 disable divider 0 overflow signal timer 0 underflow signal rc.0-3 signal s r q ief.3 evf.3 p1.2 (/int0) signal s r q ief.4 evf.4 overflow signal s r q ief.5 evf.5 serial i/o signal s r q ief.6 evf.6 p1.3(/int1) signal s r q ief.7 evf.7 underflow signal divider 1 timer 1 figure 5-8 interrupt event control diagram
w742e/c811 publication release date: april 15, 2005 - 27 - revision a2 5.15 stop mode operation in stop mode, all operations of the c cease. the c enters stop mode when the stop instruction is executed and exits stop mode when an external trigger is activated (by a falling signal on the rc or rd port). when the designated signal is accepted, the c awakens and executes the next instruction. in the dual-clock slow operation mode, the stop instruction will disable both the main-oscillator and sub-oscillator oscillating; to avoid erroneous execution, the nop instruction should follow the stop command. 5.15.1 stop mode wake-up enable flag for rc and rd port (sef) the stop mode wake-up flag for port rc and rd is organized as an 8-bit binary register (sef.0 to sef.7). before port rc and rd can be used to exit the stop mode, the content of the sef must be set first. the sef is controlled by the mov sef, #i instruction. the bit descriptions are as follows: sef www 4 5 6 w 7 www 0 1 2 w 3 note: w means write only. sef.0 = 1 device will exit stop mode when a falling edge signal is applied to pin rc.0 sef.1 = 1 device will exit stop mode when a falling edge signal is applied to pin rc.1 sef.2 = 1 device will exit stop mode when a falling edge signal is applied to pin rc.2 sef.3 = 1 device will exit stop mode when a falling edge signal is applied to pin rc.3 sef.4 = 1 device will exit stop mode when a falling edge signal is applied to pin rd.0 sef.5 = 1 device will exit stop mode when a falling edge signal is applied to pin rd.1 sef.6 = 1 device will exit stop mode when a falling edge signal is applied to pin rd.2 sef.7 = 1 device will exit stop mode when a falling edge signal is applied to pin rd.3 5.16 hold mode operation in hold mode, all operations of the c cease, except for the operation of the oscillator, timer, divider, and lcd driver. the c enters hold mode when the hold instruction is executed. the hold mode can be released in one of nine ways: by the action of timer 0, timer 1, divider 0, divider 1, rc port, p1.2 ( int0 ), serial i/o, p1.3 ( int1 ) and rd port. before the device enters the hold mode, the hef, hefd, pef, and ief flags must be set to control the hold mode release conditions. when any of the hcf bits is "1," the hold mode will be released. regarding to rc and rd port, psr0 and psr1 registers indicate signal change on which pin of the port. the hcf and hcfd are set by hardware and clear by software. when evf, evfd and hef, hefd have been reset by the clr evf,#i clr evfd and mov hef,#i clr hefd instructions, the corresponding bit of hcf, hcfd is reset simultaneously. the hcf and hcfd should be clear every time before enter the hold mode. for more details, refer to the following flow chart.
w742e/c811 - 28 - divider 0, divider 1, timer 0, timer 1, signal change at rc,rd port, falling edge at p1.2,p1.3, serial i/o in hold mode? ief flag set? pc <- (pc+1) ief flag set? no yes no yes yes no yes no hold hef flag set? reset evf flag execute interrupt service routine reset evf flag execute interrupt service routine interrupt enable? interrupt enable? yes yes no no disable interrupt disable interrupt (note) (note) note: the bit of evf corresponding to the interrupt signal will be reset. ** the rd port can not occur interrupt service , it only can release hold mode. (hold release) figure 5-9 hold mode and interrupt operation flow chart
w742e/c811 publication release date: april 15, 2005 - 29 - revision a2 5.16.1 hold mode release enable flag (hef, hefd) the hold mode release enable flag is organized on an 8-bit binary register (hef.0 to hef.7) and a 1- bit register (hefd). the hef and hefd are used to control the hold mode release conditions. it is controlled by the mov hef, #i, mov hefd,#i instructions. the bit descriptions are as follows: w 0 1 2 hef wwww 3 4 5 6 7 w ww w 0 hefd note: w means write only. hef.0 = 1 overflow from the divider 0 causes hold mode to be released. hef.1 = 1 underflow from timer 0 causes hold mode to be released. hef.2 = 1 signal change at port rc causes hold mode to be released. hef.3 = 1 falling edge signal at port p1.2 (/int0) causes hold mode to be released. hef.4 = 1 overflow from the divider 1 causes hold mode to be released. hef.5 = 1 serial i/o hef.6 = 1 falling edge signal at port p1.3 (/int1) causes hold mode to be released. hef.7 = 1 underflow from timer 1 causes hold mode to be released. hefd = 1 signal change at port rd causes hold mode to be released. 5.16.2 interrupt enable flag (ief) the interrupt enable flag is organized as a 8-bit binary register (ief.0 to ief.7). these bits are used to control the interrupt conditions. it is controlled by the mov ief, #i instruction. when one of these interrupts is occurred, the corresponding event flag will be clear, but the other bits are unaffected. in interrupt subroutine, these interrupts will be disable till the instruction mov ief, #i or en int is executed again. however, these interrupts can be disable by executing dis int instruction. the bit descriptions are as follows: w 1 2 3 ief 4 w w 5 60 w w 7 w ww note: w means write only. ief.0 = 1 interrupt 0 is accepted by overflow from the divider 0. ief.1 = 1 interrupt 1 is accepted by underflow from the timer 0. ief.2 = 1 interrupt 2 is accepted by a signal change at port rc. ief.3 = 1 interrupt 3 is accepted by a falling edge signal at port p1.2 (/int0). ief.4 = 1 interrupt 4 is accepted by overflow from the divider 1. ief.5 = 1 interrupt 5 is accepted by serial i/o signal ief.6 = 1 interrupt 6 is accepted by a falling edge signal at port p1.3 (/int1). ief.7 = 1 interrupt 7 is accepted by underflow from timer 1.
w742e/c811 - 30 - 5.16.3 port enable flag (pef, p1ef) the port enable flag is organized as 8-bit binary register (pef.0 to pef.7) and 4-bit register (p1ef.2 and p1ef.3). before port rc, rd may be used to release the hold mode, the content of the pef must be set first. the pefand p1ef are controlled by the mov pef, #i mov p1ef,#i instructions. the bit descriptions are as follows. besides release hold mode, the rc port can be bit controlled individually to perform interrupt function. pef www 4 5 6 w 7 www 0 1 2 w 3 ww- 0 1 2 - 3 p1ef note: w means write only. pef.0: enable/disable the signal change at pin rc.0 to release hold mode or perform interrupt. pef.1: enable/disable the signal change at pin rc.1 to release hold mode or perform interrupt. pef.2: enable/disable the signal change at pin rc.2 to release hold mode or perform interrupt. pef.3: enable/disable the signal change at pin rc.3 to release hold mode or perform interrupt. pef.4: enable/disable the signal change at pin rd.0 to release hold mode. pef.5: enable/disable the signal change at pin rd.1 to release hold mode. pef.6: enable/disable the signal change at pin rd.2 to release hold mode. pef.7: enable/disable the signal change at pin rd.3 to release hold mode. p1ef.2: enable/disable the falling edge signal at p1.2 to release hold mode. p1ef.3: enable/disable the falling edge signal at p1.3 to release hold mode. 5.16.4 hold mode release condition flag (hcf, hcfd) the hold mode release condition flag is organized as 8-bit binary register (hcf.0 to hcf.7) and hcfd. it indicates which one releases the hold mode, and is set by hardware. the hcf can be read out by the mova r, hcfl and mova r, hcfh instructions. when any of the hcf bits is "1," the hold mode will be released. but the hcfd can not be read, it is only for internal flag. it records the port rd releasing the hold mode. the hcf and hcfd are set by hardware and clear by software. the hcf and hcfd should be clear every time before enter the hold mode. when evf, evfd and hef, hefd have been reset, the corresponding bit of hcf, hcfd is reset simultaneously. the bit descriptions are as follows: rr hcf 0 1 2 3 4 5 r r r 6 7 rr r hcfd: internal flag, can not be read note: r means read only.
w742e/c811 publication release date: april 15, 2005 - 31 - revision a2 hcf.0 = 1 hold mode was released by overflow from the divider 0. hcf.1 = 1 hold mode was released by underflow from the timer 0. hcf.2 = 1 hold mode was released by a signal change at port rc. hcf.3 = 1 hold mode was released by a signal change at port p1.2 (/int0). hcf.4 = 1 hold mode was released by overflow from the divider 1. hcf.5 = 1 hold mode was released by serial i/o signal. hcf.6 = 1 hold mode was released by a signal change at port p1.3 (/int1). hcf.7 = 1 hold mode was released by underflow from the timer 1. hcfd = 1 hold mode was released by a signal change at port rd. 5.16.5 event flag (evf,evfd) the event flag is organized as a 8-bit binary register (evf.0 to evf.7) and evfd. it is set by hardware and reset by clr evf,#i ,clr evfd instructions or the interrupt occurrence. the bit descriptions are as follows: r/w r/w r/w evf 0 1 2 3 4 5 r/w 6 7 r/w r/w r/w evfd r/w r/w note: r/w means read/write. evf.0 = 1 overflow from divider 0 occurred. evf.1 = 1 underflow from timer 0 occurred. evf.2 = 1 signal change at port rc occurred. evf.3 = 1 falling edge signal at port p1.2 ( int0 ) occurred. evf.4 = 1 overflow from divider 1 occurred. evf.5 = 1 serial i/o occurred. evf.6 = 1 falling edge signal at port p1.3 ( int1 ) occurred. evf.7 = 1 underflow from timer 1 occurred. evfd = 1 signal change at port rd occurred.
w742e/c811 - 32 - 5.17 reset function the w742e/c811 is reset either by a power-on reset or by using the external res pin. the initial state of the w742e/c811 after the reset function is executed is described below. table 3 the initial state after the reset function is executed program counter (pc) 000h tm0, tm1 reset mr0, mr1, page registers reset psr0, psr1, psr2, scr registers reset ief, hef,hefd, hcf, pef, p1ef, evf, evfd, sef flags reset wrp, dbkr register reset timer 0 input clock f osc /4 timer 1 input clock f osc mfp output low dtmf output hi-z input/output ports ra,rb, p0 input mode output port re & rf high ra, rb & p0 ports output type cmos type rc,rd ports pull-high resistors disable input clock of the watchdog timer f osc /1024 lcd display off 5.18 input/output ports ra, rb & p0 port ra consists of pins ra.0 to ra.3. port rb consists of pins rb.0 to rb.3. port p0 consists of pins p0.0 to p0.3. at initial reset, input/output ports ra, rb and p0 are all in input mode. when ra and rb are used as output ports, cmos or nmos open drain output type can be selected by the pm0 register. but when p0 is used as output port, the output type is just fixed to be cmos output type. each pin of port ra, rb and p0 can be specified as input or output mode independently by the pm1, pm2 and pm6 registers. the mova r, ra or mova r, rb or mova r, p0 instructions operate the input functions and the mov ra, r or mov rb, r or mov p0, r operate the output functions. for more detail port structure, refer to the and figure 5-10 and figure 5-10.
w742e/c811 publication release date: april 15, 2005 - 33 - revision a2 input/output pin of the ra(rb) i/o pin ra.n(rb.n) data bus buffer output pm0.0(pm0.1) pm1.n (pm2.n) mova r,ra(mova r,rb) instruction mov ra,r(mov rb,r) instruction enable enable figure 5-10 architecture of ra (rb) input/output pins input/output pin of the p0 i/o pin p0.n data bus buffer output pm6.n mova r,p0 instruction mov p0,r instruction enable enable figure 5-11 architecture of p0 input/output pins 5.18.1 port mode 0 register (pm0) the port mode 0 register is organized as 4-bit binary register (pm0.0 to pm0.3). pm0 can be used to determine the port structure; it is controlled by the mov pm0, #i instruction. the bit description is as follows: pm0 www 0 1 2 w 3 note: w means write only. bit 0 = 0 ra port is cmos output type. bit 0 = 1 ra port is nmos open drain output type. bit 1 = 0 rb port is cmos output type. bit 1 = 1 rb port is nmos open drain output type. bit 2 = 0 rc port pull-high resistor is disabled. bit 2 = 1 rc port pull-high resistor is enabled. bit 3 = 0 rd port pull-high resistor is disabled. bit 3 = 1 rd port pull-high resistor is enabled.
w742e/c811 - 34 - 5.18.2 port mode 1 register (pm1) the port mode 1 register is organized as 4-bit binary register (pm1.0 to pm1.3). pm1 can be used to control the input/output mode of port ra. pm1 is controlled by the mov pm1, #i instruction. the bit description is as follows: pm1 www 0 1 2 w 3 note: w means write only. bit 0 = 0 ra.0 works as output pin; bit 0 = 1 ra.0 works as input pin bit 1 = 0 ra.1 works as output pin; bit 1 = 1 ra.1 works as input pin bit 2 = 0 ra.2 works as output pin; bit 2 = 1 ra.2 works as input pin bit 3 = 0 ra.3 works as output pin; bit 3 = 1 ra.3 works as input pin at initial reset, port ra is input mode (pm1 = 1111b). 5.18.3 port mode 2 register (pm2) the port mode 2 register is organized as 4-bit binary register (pm2.0 to pm2.3). pm2 can be used to control the input/output mode of port rb. pm2 is controlled by the mov pm2, #i instruction. the bit description is as follows: pm2 www 0 1 2 w 3 note: w means write only. bit 0 = 0 rb.0 works as output pin; bit 0 = 1 rb.0 works as input pin bit 1 = 0 rb.1 works as output pin; bit 1 = 1 rb.1 works as input pin bit 2 = 0 rb.2 works as output pin; bit 2 = 1 rb.2 works as input pin bit 3 = 0 rb.3 works as output pin; bit 3 = 1 rb.3 works as input pin at initial reset, the port rb is input mode (pm2 = 1111b). 5.18.4 port mode 6 register (pm6) the port mode 6 register is organized as 4-bit binary register (pm6.0 to pm6.3). pm6 can be used to control the input/output mode of port p0. pm6 is controlled by the mov pm6, #i instruction. the bit description is as follows: pm6 www 0 1 2 w 3 note: w means write only.
w742e/c811 publication release date: april 15, 2005 - 35 - revision a2 bit 0 = 0 p0.0 works as output pin; bit 0 = 1 p0.0 works as input pin bit 1 = 0 p0.1 works as output pin; bit 1 = 1 p0.1 works as input pin bit 2 = 0 p0.2 works as output pin; bit 2 = 1 p0.2 works as input pin bit 3 = 0 p0.3 works as output pin; bit 3 = 1 p0.3 works as input pin at initial reset, the port p0 is input mode (pm6 = 1111b). 5.18.5 serial i/o interface the bit 0 and bit 1 of port p0 can be used as a serial input/output port. p0.0 is the serial clock i/o pin and p0.1 is the serial data i/o pin. a 4-bit binary register, serial interface control register (sic), controls the serial port. sic is controlled by the mov sic,#i instruction. the bit definition is as follow: sic www 0 1 2 w 3 bit 0 = 0 p0.0 & p0.1 work as normal input/output pin; bit 0 = 1 p0.0 & p0.1 work as serial port function. bit 1 = 0 p0.0 works as serial clock input pin; bit 1 = 1 p0.0 works as serial clock output pin. bit 2 = 0 serial data latched/cha nged at falling edge of clock; bit 2 = 1 serial data latched/changed at rising edge of clock. bit 3 = 0 serial clock output frequency is fosc/2; bit 3 = 1 serial clock output frequency is fosc/256. at initial reset, sic = 0000b. the serial i/o functions are controlled by the instructions sop r and sip r . the two instructions are described below: (1) when in the first time the sip r instruction is executed, the data will be loaded to the acc and ram from the serial input buffer. but this data is not meaningful, it is used to enable serial port. there are two methods to get the serial data, one is interrupt and the other is polling. when enable the serial input, the bit 1 of port status register 2(prs2) will automatically be set to "1" (busy i = 1). then the p0.0 pin will send out 8 clocks or accept 8 clcoks from external device and the data from the p0.1 pin will be loaded to si b buffer at the rising or falling edge of the p0.0 pin. after the 8 clocks have been sent, busy i will be reset to "0" and evf.5 will be set to "1." at this time, if ief.5 has been set (ief.5 = 1), an interrupt is executed then the sip r instruction can get the correct data from the serial input buffer (sib), low nibble of sib movs to acc register and the high nibble moves to ram ; if hef.5 has been set (hef.5 = 1), the hold state is terminated. the polling method is to check the status of psr2.1 (busy i ) to know whether the serial input process is completed or not. if a serial input process is not completed, but the sip r instruction is executed again, the data will be lost. the timing is shown in figure 5-12.
w742e/c811 - 36 - t1 t2 t3 t4 p0.0 data latch busyi (psr2.1) evf5 ins. p0.1 123 4 5678 123 4 5678 rising latch p0.0 falling latch note: the serial clock frequency is fosc/2 sip r figure 5-12 timing of the serial input function (sip r) (2) when the sop r instruction is executed, the data will be loaded to the serial output buffer (sob) from acc and the ram, the low nibble data of sob is from acc register and the high nibble data is from ram, and bit 3 of port status register 2(psr2) will be set to "1" (busy o = 1). then the p0.0 pin will send out 8 clocks or accept 8 clocks from external device and the data in sob will be sent out at the rising or falling edge of the p0.1 pin. after the 8 clocks have been sent, busy o will be reset to "0" and evf.5 will be set to "1." at this time, if ief.5 has been set (ief.5 = 1), an interrupt is executed; if hef.5 has been set (hef.5 = 1), the hold state is terminated. users can check the status of psr2.3 (busy o ) to know whether the serial output process is completed or not. if a serial output process is not completed, but the sop r inst ruction is executed again, the data will be lost. the timing is shown in figure 5-13.
w742e/c811 publication release date: april 15, 2005 - 37 - revision a2 t1 t2 t3 t4 p0.0 data latch busyo (psr2.3) evf5 ins. p0.1 123 4 5678 123 4 5678 data changed at falling edge p0.0 note: the serial clock frequency is fosc/2 sop r data changed at rising edge figure 5-13 timing of the serial output function (sop r) port status register 2 (psr2) port status register 2 is organized as 4-bit binary register (psr2.0 to psr2.3). psr2 is controlled by the mova r, psr2, and clr psr2 instructions. the bit descriptions are as follows: rr 0 1 2 3 psr2 note: r means read only. bit 0 is reserved. bit 1 (busyi ): serial port input busy flag. bit 2 is reserved. bit 3 (busyo ): serial port output busy flag. 5.19 input ports rc port rc consists of pins rc.0 to rc.3. each pin of port rc can be connected to a pull-high resistor, which is controlled by the port mode 0 register (pm0). when the pef, hef, and ief corresponding to the rc port are set, a signal change at the specified pins of port rc will execute the hold mode
w742e/c811 - 38 - release or interrupt subroutine. port status register 0 (psr0) records the status of signal changes on the pins of port rc. psr0 can be read out and cleared by the mova r, psr0 , and clr psr0 instructions. in addition, the fallin g edge signal on the pin of port rc specified by the instruction mov sef, #i will cause the device to exit the stop mode . refer to figure 5-14 and the instruction table for more details. signal change detector pef.0 d ck q r psr0.0 psr0.2 d ck q r data bus rc.0 psr0.3 d ck q r pef.3 reset clr psr0 hcf.2 int 2 reset clr evf, #i evf.2 hef.2 ief.2 falling edge detector falling edge detector falling edge detector falling edge detector sef.0 sef.1 sef.2 sef.3 to wake up stop mode signal change detector d ck q r psr0.1 rc.1 pef.1 signal change detector d ck q r pef.2 rc.2 signal change detector rc.3 mov pef, #i pm0.2 pm0.2 pm0.2 pm0.2 figure 5-14 architecture of input ports rc
w742e/c811 publication release date: april 15, 2005 - 39 - revision a2 5.19.1 port status register 0 (psr0) port status register 0 is organized as 4-bit binary register (psr0.0 to psr0.3). psr0 can be read or cleared by the mova r, psr0 , and clr psr0 instructions. the bit descriptions are as follows: r rrr 0 1 2 3 psr0 note: r means read only. bit 0 = 1 signal change at rc.0 bit 1 = 1 signal change at rc.1 bit 2 = 1 signal change at rc.2 bit 3 = 1 signal change at rc.3 5.20 input ports rd port rd consists of pins rd.0 to rd.3. each pin of port rd can be connected to a pull-high resistor, which is controlled by the port mode 0 register (pm0). when the pef and hefd corresponding to the rd port are set, a signal change at the specified pins of port rd will execute the hold mode release. port status register 1 (psr1) records the status of signal changes on the pins of port rd. psr1 can be read out and cleared by the mova r, psr1 , and clr psr1 instructions. in addition, the falling edge signal on the pin of port rd specified by the instruction mov sef, #i will cause the device to exit the stop mode . refer to figure 5-15 and the in struction table for more details.
w742e/c811 - 40 - signal change detector pef.4 d ck q r psr1.0 psr1.2 d ck q r data bus rd.0 psr1.3 d ck q r pef.7 reset clr psr1 hcfd reset clr evfd evfd hefd falling edge detector falling edge detector falling edge detector falling edge detector sef.4 sef.5 sef.6 sef.7 to wake up stop mode signal change detector d ck q r psr1.1 rd.1 pef.5 signal change detector d ck q r pef.6 rd.2 signal change detector rd.3 pm0.3 pm0.3 pm0.3 pm0.3 mov pef, #i figure 5-15 architecture of input ports rd 5.20.1 port status register 1 (psr1) port status register 1 is organized as 4-bit binary register (psr1.0 to psr1.3). psr1 can be read or cleared by the mova r, psr1, and clr psr1 instructions. the bit descriptions are as follows: r rrr 0 1 2 3 psr1 note: r means read only.
w742e/c811 publication release date: april 15, 2005 - 41 - revision a2 bit 0 = 1 signal change at rd.0 bit 1 = 1 signal change at rd.1 bit 2 = 1 signal change at rd.2 bit 3 = 1 signal change at rd.3 5.21 output port re & rf output port re and rf are used as output of the internal rt port. when the mov re, r or mov rf, r instruction is executed, the data in the ram will be output to port rt thro ugh port re or rf. they provide high sink current to drive led. 5.22 input port p1 input port p1 is a multi-function input port. when the mova r, p1 instruction is executed, the p1 data will be get to the ram and a regist er. the p1.2 and p1.3 can be configur ated as the external interrupt /int0 and /int1 by set p1ef.2 and p1ef.3. 5.23 dtmf output pin (dtmf) w742e/c811 provides a dtmf generator which outputs the dual tone multi-frequency signal to the dtmf pin. the dtmf generator can work well at the operating frequency of 3.58 mhz. a dtmf register specify the desired low/high frequency. and the dual tone control register (dtcr) can control whether the dual tone will be output or no t. the tones are divided in to two groups (low group and high group). the relation between the dtmf signal and the corresponding touch tone keypad is shown in figure 5-16. row/col frequency r1 697 hz r2 770 hz r3 852 hz r4 941 hz c1 1209 hz c2 1336 hz c3 1477 hz c4 1633 hz figure 5-16 the relation between the touch tone keypad and the frequency 1 2 3 a 4 5 6 b 7 8 9 c * 0 # d r1 r2 r3 r4 c1 c2 c3 c4
w742e/c811 - 42 - 5.23.1 dtmf register dtmf register is organized as 4-bit binary register. by controlling the dtmf register, one tone of the low/high group can be selected. the mov dtmf, r instruction can specify the wanted tones. the bit descriptions are as follows: w www 0 1 2 3 dtmf note: w means write only. b3 b2 b1 b0 selected tone x x 0 0 1209 hz high x x 0 1 1336 hz group x x 1 0 1477 hz x x 1 1 1633 hz 0 0 x x 697 hz low 0 1 x x 770 hz group 1 0 x x 852 hz 1 1 x x 941 hz note: x means this bit do not care. 5.23.2 dual tone control register (dtcr) dual tone control register is organized as 4-bit binary register. the output of the dual or single tone will be controlled by this register. the mov dtcr,#i instruction can specify the wanted status. the bit descriptions are as follows: www 0 1 2 3 dtcr note: w means write only. bit 0 = 1 low group tone output is enabled. bit 1 = 1 high group tone output is enabled. bit 2 = 1 dtmf output is enabled. when bit 2 is reset to 0, the dtmf output pin will be hi-z state. bit 3 is reserved. 5.24 mfp output pin (mfp) the mfp output pin can select the output of the timer 1 clock or the modulation frequency; the output of the pin is determined by mode register 1 (mr1). the organization of mr1 is shown in figure 5-7. when bit 2 of mr1 is reset to "0," the mfp output can deliver a modulation output in any combination
w742e/c811 publication release date: april 15, 2005 - 43 - revision a2 of one signal from among dc, 4096 hz, 2048 hz, and one or more signals from among 128 hz, 64 hz, 8 hz, 4 hz, 2 hz, or 1 hz (the clock source is from 32.768 khz crystal). the mov mfp, #i instruction is used to specify the modulation output combination. the data specified by the 8-bit operand and the mfp output pin are shown in next page. table 4 the relation between the mfp output frequncy and the data specified by 8-bit operand (fosc = 32.768 khz) r7 r6 r5 r4 r3 r2 r1 r0 function 0 0 0 0 0 0 low level 0 0 0 0 0 1 128 hz 0 0 0 0 1 0 64 hz 0 0 0 0 0 1 0 0 8 hz 0 0 1 0 0 0 4 hz 0 1 0 0 0 0 2 hz 1 0 0 0 0 0 1 hz 0 0 0 0 0 0 high level 0 0 0 0 0 1 128 hz 0 0 0 0 1 0 64 hz 0 1 0 0 0 1 0 0 8 hz 0 0 1 0 0 0 4 hz 0 1 0 0 0 0 2 hz 1 0 0 0 0 0 1 hz 0 0 0 0 0 0 2048 hz 0 0 0 0 0 1 2048 hz * 128 hz 0 0 0 0 1 0 2048 hz * 64 hz 1 0 0 0 0 1 0 0 2048 hz * 8 hz 0 0 1 0 0 0 2048 hz * 4 hz 0 1 0 0 0 0 2048 hz * 2 hz 1 0 0 0 0 0 2048 hz * 1 hz 0 0 0 0 0 0 4096 hz 0 0 0 0 0 1 4096 hz * 128 hz 0 0 0 0 1 0 4096 hz * 64 hz 1 1 0 0 0 1 0 0 4096 hz * 8 hz 0 0 1 0 0 0 4096 hz * 4 hz 0 1 0 0 0 0 4096 hz * 2 hz 1 0 0 0 0 0 4096 hz * 1 hz
w742e/c811 - 44 - 5.25 lcd controller/driver the w742e/c811 can directly drive an lcd with 40 segment output pins and 16 common output pins for a total of 40 16 dots. the lcd driving mode is 1/5 bias 1/8 or 1/16 duty. the alternating frequency of the lcd can be set as fw/16, fw/32, fw/64, or fw/128. the structure of the lcd alternating frequency (f lcd ) is shown in the figure 5-17. q1 q2 q3 q4 q5 q6 q7 q8 q9 fw selector fw/128 fw/64 fw/32 fw/16 sub-oscillator clock f lcd figure 5-17 lcd alternating frequency (flcd) circuit diagram fw = 32.768 khz, the lcd frequency is as shown in the table below. table 5 the relartionship between the f lcd and the duty cycle lcd frequency 1/8 duty 1/16 duty fw/128 (256 hz) 32 - fw/64 (512 hz) 64 32 fw/32 (1024 hz) 128 64 fw/16 (2048 hz) - 128
w742e/c811 publication release date: april 15, 2005 - 45 - revision a2 corresponding to the 40 lcd drive output pins, there are 160 lcd data ram segments. instructions such as mov lpl,r, mov lph,r, mov @lp,r, and mov r,@lp are used to control the lcd data ram. the data in the lcd data ram are transferred to the segment output pins automatically without program control. when the bit value of the lcd data ram is "1," the lcd is turned on. when the bit value of the lcd data ram is "0," lcd is turned off. the contents of the lcd data ram (lcdr) are sent out through the segment0 to segment39 pins by a direct memory access. the relation between the lcd data ram and segment/common pins is shown below. table 6 the reation between the lcdr and segment/common pins used as lcd drive output pins output lcd com7 com6 com5 com4 lcd com3 com2 com1 com0 pin ram bit3 bit2 bit1 bit0 ram bit3 bit2 bit1 bit0 seg0 lcdr01 0/1 0/1 0/1 0/1 lcdr00 0/1 0/1 0/1 0/1 seg1 lcdr03 0/1 0/1 0/1 0/1 lcdr02 0/1 0/1 0/1 0/1 : : : : : : : : : : : : : : : : : : : : : : seg38 lcdr4d 0/1 0/1 0/1 0/1 lcdr4c 0/1 0/1 0/1 0/1 seg39 lcdr4f 0/1 0/1 0/1 0/1 lcdr4e 0/1 0/1 0/1 0/1 output lcd com15 com14 com13 com12 lcd com11 com10 com9 com8 pin ram bit3 bit2 bit1 bit0 ram bit3 bit2 bit1 bit0 seg0 lcdr81 0/1 0/1 0/1 0/1 lcdr80 0/1 0/1 0/1 0/1 seg1 lcdr83 0/1 0/1 0/1 0/1 lcdr82 0/1 0/1 0/1 0/1 : : : : : : : : : : : : : : : : : : : : : : seg38 lcdrcd 0/1 0/1 0/1 0/1 lcdrcc 0/1 0/1 0/1 0/1 seg39 lcdrcf 0/1 0/1 0/1 0/1 lcdrce 0/1 0/1 0/1 0/1 the lcdon instruction turns the lcd display on (even in hold mode), and the lcdoff instruction turns the lcd display off. at the init ial reset state, the lcd display is turned off automatically. to turn on the lcd display, the instruction lcdon must be executed. 5.25.1 lcd ram addressing method there are 160 lcd rams (lcdr00h - lcdr4fh, lcdr80h - lcdr0cfh) that should be indirectly addressed. the lcd ram pointer (lp) is used to point to the address of the wanted lcd ram but it is not readable . the lp is organized as 8-bit binary register. the mov lpl,r and mov lph,r instructions can load the lcd ram address from ram to the lp register. the mov @lp,r and mov r,@lp instructions can access the pointed lcd ram content.
w742e/c811 - 46 - 5.25.2 lcd voltage and contrast adjusting lcd power (vlcd2) has two source, one is directly from the vlcd1 pin, another is from internal pump circuit. the lcd power source is selected by mask option. the pump circuit doubles the c input voltage (v dd ), the power consumption in internal pump mode is more than directly input from vlcd1 . the lcd pump circuit only works in the vdd range from 2.4v to 4.0v. if the operating voltage of vdd is up 4.0v, the lcd power should come from the vlcd1 pin. the lcd contrast is adjustable by an internal variable resistor (vr). vlcd voltage is controlled by setting bit2, bit1 and bit0 of lcd contrast control register (lcdcc). lcdcc is determined by executing mov lcdcc,#i . the figure 5-18 shows the ldc power control as below: vdd cp cn vlcd1 internal pump circuit vlcd2 vlcd v3 v2 v1 v4 vss stop lcdoff code option en s1 vr note: vr is determined by lcdcc register r r r r r outside chip inside chip figure 5-18 lcd power control circuit www 0 1 2 3 lcdcc note: w means write only. lcdcc vlcd/vlcd2 0000h 1.00 0001h 0.96 0010h 0.93 0011h 0.89 0100h 0.86 0101h 0.81 0110h 0.76 0111h 0.71 bit 3 is reserved.
w742e/c811 publication release date: april 15, 2005 - 47 - revision a2 5.25.3 seg32-seg39 using as dc output (nmos open drain type) seg32-seg39 pins output type can be changed to dc output mode by code mask option. the correspoinding control resigters are lcd ram address lcdr40 and lcdr41, these two parts are individually enabled by code mask option. lcdr40 controls the seg32-seg35 pins and lcdr41 controls the seg36- seg39 pins. when seg32-seg39 are used as dc output, their output type is nmos open drain type. the instruction mov @lp,r outputs the ram data to seg32-39, when seg32-39 operate in dc output mode. 5.25.4 the output waveforms for the lcd driving mode 1/5 bias 1/8 (1/16) duty lighting system (example) normal operating mode com0 v3 v4 vss v2 v1 vlcd 4 3 2 1 8 (16) 4 3 2 18 (16) " " " " " " " " " " " " " " " " " " v3 v4 vss v2 v1 vlcd seg " " " v3 v4 vss v2 v1 vlcd -v4 -v3 -v2 -v1 -vlcd lcd driver outputs for seg. on com0 side being lit " " "
w742e/c811 - 48 - 6. absolute maximum ratings parameter rating unit supply voltage to ground potential -0.3 to +7.0 v applied input/output voltage -0.3 to +7.0 v power dissipation 120 mw ambient operating temperature 0 to +70 c storage temperature -55 to +150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. 7. dc characteristics (v dd ? v ss = 3.0v, fm = 3.58 mhz, fs = 32.768 khz, t a = 25 c, lcd on, internal pump disable; unless otherwise specified) parameter sym. conditions min. typ. max. unit op. voltage (w742c811) v dd - 2.4 - 5.5 v op. voltage (W742E811) v dd - 2.4 - 4.8 v op. current (crystal type) i op1 no load (ext-v) in dual-clock normal operatio - 0.5 1.0 ma op. current (crystal type) i op3 no load (ext-v) in dual-clock slow operation and fm is stopped - 30 50 a hold current (crystal type) i hm1 hold mode no load (ext-v) in dual-clock normal operation - 400 500 a hold current (crystal type) i hm3 hold mode no load (ext-v) in dual-clock slow operation and fm is stopped - 30 50 a hold current (crystal type) i hm5 hold mode no load (ext-v) v dd =5v; in dual-clock slow operation and fm is stopped - 50 80 a stop current i sm1 stop mode no load (ext-v) fm and fs are stopped - 1 2 a input low voltage v il - vss - 0.3 v dd v input high voltage v ih - 0.7 v dd - v dd v mfp output low voltage v ml i ol = 3.5 ma - - 0.4 v mfp output high voltage v mh i oh = 3.5 ma 2.4 - - v
w742e/c811 publication release date: april 15, 2005 - 49 - revision a2 dc characteristics, continued parameter sym. conditions min. typ. max. unit port ra, rb, rd output low voltage v abl i ol = 2.0 ma - - 0.4 v port ra, rb, rd output high voltage v abh i oh = 2.0 ma 2.4 - - v lcd supply current i lcd all seg. on - - 20 a seg0 ? seg39 sink current (used as lcd output) i ol1 v ol = 0.4v v lcd = 0.0v 90 - - a seg0 ? seg39 drive current (used as lcd output) i oh1 v oh = 2.4v v lcd = 3.0v 90 - - a port re, rf sink current i el v ol = 0.9v 9 - - ma port re, rf source current i eh v oh = 2.4v 0.4 1.2 - ma dtmf output dc level v tdc r l = 5 k ? , v dd = 2.5 to 3.8v 1.1 - 2.8 v dtmf distortion thd r l = 5 k ? , v dd = 2.5 to 3.8v - -30 -23 db dtmf output voltage v to low group, r l = 5 k ? 130 150 170 mvrms pre-emphasis col/row 1 2 3 db pull-up resistor r c port rc 100 350 1000 k ? res pull-up resistor r res - 20 100 500 k ? 8. ac characteristics parameter sym. conditions min. typ. max. unit op. frequency f osc rc type - 2000 - khz crystal type - 3.58 - mhz frequency deviation by voltage drop for rc oscillator ? f f f(3v) - f(2.4v) f(3v) - - 10 % instruction cycle time t i one machine cycle - 4/f osc - s reset active width t raw f osc = 32.768 khz 1 - - s interrupt active width t iaw f osc = 32.768 khz 1 - - s
w742e/c811 - 50 - 9. instruction set table symbol description acc: accumulator acc.n: accumulator bit n wr: working register wrp: wr page register page: page register dbkrl: data bank register (low nibble) dbkrh: data bank register (high nibble) rompr: rom page register mr0: mode register 0 mr1: mode register 1 pm0: port mode 0 pm1: port mode 1 pm4: port mode 4 pm5: port mode 5 pm6: port mode 6 psr0: port status register 0 psr1: port status register 1 psr2: port status register 2 r: memory (ram) of address r lp: lcd data ram pointer lpl: low nibble of the lcd data ram pointer lph: high nibble of the lcd data ram pointer r.n: memory bit n of address r i: constant parameter l: branch or jump address cf: carry flag zf: zero flag pc: program counter
w742e/c811 publication release date: april 15, 2005 - 51 - revision a2 continued tm0l: low nibble of the timer 0 counter tm0h: high nibble of the timer 0 counter tm1l: low nibble of the timer 1 counter tm1h: high nibble of the timer 1 counter lcdcc lcd contrast control register tab0: look-up table address buffer 0 tab1: look-up table address buffer 1 tab2: look-up table address buffer 2 tab3: look-up table address buffer 3 ief.n: interrupt enable flag n hcf.n: hold mode release condition flag n hef.n: hold mode release enable flag n hefd: rd port hold mode release enable flag sef.n: stop mode wake-up enable flag n pef.n: port enable flag n p1ef.n: p1 port enable flag n evf.n: event flag n evfd: rd port event flag n ! =: not equal &: and ^: or ex: exclusive or : transfer direction, result [page*10h+()]: contents of address page (bit2, bit1, bit0)*10h+() [p()]: contents of port p
w742e/c811 - 52 - machine code mnemonic function flag affected w/c arithmetic 0001 1000 0xxx xxxx add r, acc acc (r) + (acc) zf, cf 1/1 0001 1100 i i i i nnnn add wrn, #i acc (wrn) + i zf, cf 1/1 0001 1001 0xxx xxxx addr r, acc acc, r (r) + (acc) zf, cf 1/1 0001 1101 i i i i nnnn addr wrn, #i acc, wrn (wrn) + i zf, cf 1/1 0000 1000 0xxx xxxx adc r, acc acc (r) + (acc) + (cf) zf, cf 1/1 0000 1100 i i i i nnnn adc wrn, #i acc (wrn) + i + (cf) zf, cf 1/1 0000 1001 0xxx xxxx adcr r, acc acc, r (r) + (acc) + (cf) zf, cf 1/1 0000 1101 i i i i nnnn adcr wrn, #i acc, wrn (wrn) + i + (cf) zf, cf 1/1 0010 1000 0xxx xxxx adu r, acc acc (r) + (acc) zf 1/1 0010 1100 i i i i nnnn adu wrn, #i acc (wrn) + i zf 1/1 0010 1001 0xxx xxxx adur r, acc acc, r (r) + (acc) zf 1/1 0010 1101 i i i i nnnn adur wrn, #i acc, wrn (wrn) + i zf 1/1 0001 1010 0xxx xxxx sub r, acc acc (r) - (acc) zf, cf 1/1 0001 1110 i i i i nnnn sub wrn, #i acc (wrn) - i zf, cf 1/1 0001 1011 0xxx xxxx subr r, acc acc, r (r) - (acc) zf, cf 1/1 0001 1111 i i i i nnnn subr wrn, #i acc, wr (wr) - i zf, cf 1/1 0000 1010 0xxx xxxx sbc r, acc acc (r) - (acc) - (cf) zf, cf 1/1 0000 1110 i i i i nnnn sbc wrn, #i acc (wrn) - i - (cf) zf, cf 1/1 0000 1011 0xxxxxxx sbcr r, acc acc, r (r) - (acc) - (cf) zf, cf 1/1 0000 1111 i i i i nnnn sbcr wrn, #i acc, wrn (wrn) - i - (cf) zf, cf 1/1 0100 1010 0xxx xxxx inc r acc, r (r) + 1 zf, cf 1/1 0100 1010 1xxx xxxx dec r acc, r (r) - 1 zf, cf 1/1
w742e/c811 publication release date: april 15, 2005 - 53 - revision a2 instruction set, continued machine code mnemonic function flag affected w/c logic 0010 1010 0xxx xxxx anl r, acc acc (r) & (acc) zf 1/1 0010 1110 i i i i nnnn anl wrn, #i acc (wrn) & i zf 1/1 0010 1011 0xxx xxxx anlr r, acc acc, r (r) & (acc) zf 1/1 0010 1111 i i i i nnnn anlr wrn, #i acc, wrn (wrn) & i zf 1/1 0011 1010 0xxx xxxx orl r, acc acc (r) (acc) zf 1/1 0011 1110 i i i i nnnn orl wrn, #i acc (wrn) i zf 1/1 0011 1011 0xxx xxxx orlr r, acc acc, r (r) (acc) zf 1/1 0011 1111 i i i i nnnn orlr wrn, #i acc, wrn (wrn) i zf 1/1 0011 1000 0xxx xxxx xrl r, acc acc (r) ex (acc) zf 1/1 0011 1100 i i i i nnnn xrl wrn, #i acc (wrn) ex i zf 1/1 0011 1001 0xxx xxxx xrlr r, acc acc, r (r) ex (acc) zf 1/1 0011 1101 i i i i nnnn xrlr wrn, #i acc, wrn (wrn) ex i zf 1/1 branch 0111 0 aaa aaaa aaaa jmp l pc13~pc0 (rompr) 800h+l10~l0 1/1 1000 0 aaa aaaa aaaa jb0 l pc10~pc0 l10~l0; if acc.0 = "1" 1/1 1001 0 aaa aaaa aaaa jb1 l pc10~pc0 l10~l0; if acc.1 = "1" 1/1 1010 0 aaa aaaa aaaa jb2 l pc10~pc0 l10~l0; if acc.2 = "1" 1/1 1011 0 aaa aaaa aaaa jb3 l pc10~pc0 l10~l0; if acc.3 = "1" 1/1 1110 0 aaa aaaa aaaa jz l pc10~pc0 l10~l0; if acc = 0 1/1 1100 0 aaa aaaa aaaa jnz l pc10~pc0 l10~l0; if acc ! = 0 1/1 1111 0 aaa aaaa aaaa jc l pc10~pc0 l10~l0; if cf = "1" 1/1 1101 0 aaa aaaa aaaa jnc l pc10~pc0 l10~l0; if cf ! = "1" 1/1 0100 1000 0xxx xxxx dskz r acc, r (r) - 1; pc (pc) + 2 if acc = 0 zf, cf 1/1 0100 1000 1xxx xxxx dsknz r acc, r (r) - 1; pc (pc) + 2 if acc ! = 0 zf, cf 1/1 1010 1000 0xxx xxxx skb0 r pc (pc) + 2 if r.0 = "1" 1/1 1010 1000 1xxx xxxx skb1 r pc (pc) + 2 if r.1 = "1" 1/1 1010 1001 0xxx xxxx skb2 r pc (pc) + 2 if r.2 = "1" 1/1 1010 1001 1xxx xxxx skb3 r pc (pc) + 2 if r.3 = "1" 1/1
w742e/c811 - 54 - instruction set, continued machine code mnemonic function flag affected w/c subroutine 0110 0 aaa aaaa aaaa call l stack (pc)+1, tab0, tab1, tab2, tab3, dbkrl,dbkrh,wrp,rompr,page,acc,cf pc13 ~ pc0 (rompr) 800h+l10 ~ l0 1/1 0000 0001 0000 0000 rtn pop pc 1/1 0000 0001 i i i i i i i i rtn # i pop pc; pop other registers by i setting refer to below table 1/1 bit definition of i i = 0000 0000 pop pc from stack only bit0 = 1 pop tab0, tab1, tab2, tab3 from stack bit1 = 1 pop dbkrl, dbkrh from stack bit2 = 1 pop wrp from stack bit3 = 1 pop rompr from stack bit4 = 1 pop page from stack bit5 = 1 pop acc from stack bit6 = 1 pop cf from stack
w742e/c811 publication release date: april 15, 2005 - 55 - revision a2 instruction set, continued instruction set contin ued instruction set flag affected w/c data move 1110 1nnn nxxx xxxx mov wrn, r wrn (r) 1/1 1111 1nnn nxxx xxxx mov r, wrn r (wrn) 1/1 0110 1nnn nxxx xxxx mova wrn, r acc, wrn (r) zf 1/1 0111 1nnn nxxx xxxx mova r, wrn acc, r (wrn) zf 1/1 0101 1001 1xxx xxxx mov r, acc r (acc) 1/1 0100 1110 1xxx xxxx mov acc, r acc (r) zf 1/1 1011 1 i i i i xxx xxxx mov r, #i r i 1/1 1100 1nnn n000 qqqq mov wrn, @wrq wrn [(dbkrh)x800h+(dbkrl) 8 0h+(page)x10h +(wrq)] 1/2 1101 1nnn n000 qqqq mov @wrq, wrn [(dbkrh)x800h+(dbkrl) 80h+(pa ge)x10h +(wrq)] wrn 1/2 1000 1100 0xxx xxxx mov tab0, r tab0 (r) 1/1 1000 1100 1xxx xxxx mov tab1, r tab1 (r) 1/1 1000 1110 0xxx xxxx mov tab2, r tab2 (r) 1/1 1000 1110 1xxx xxxx mov tab3, r tab3 (r) 1/1 1000 1101 0xxx xxxx movc r r [(tab3) 1000h+(tab2) 100h+( tab1) x10h + (tab0)]/4 1/2 input & output 0101 1011 0xxx xxxx mova r, ra acc, r [ra] zf 1/1 0101 1011 1xxx xxxx mova r, rb acc, r [rb] zf 1/1 0100 1011 0xxx xxxx mova r, rc acc, r [rc] zf 1/1 0100 1011 1xxx xxxx mova r, rd acc, r [rd] zf 1/1 0101 1100 0xxx xxxx mova r, p0 acc, r [p0] zf 1/1 0101 1100 0xxx xxxx mova r, p1 acc, r [p1] zf 1/1 0101 1010 0xxx xxxx mov ra, r [ra] (r) 1/1 0101 1010 1xxx xxxx mov rb, r [rb] (r) 1/1 1010 1100 0xxx xxxx mov rc, r [rc] (r) 1/1 1010 1100 1xxx xxxx mov rd, r [rd] (r) 1/1 0101 1110 0xxx xxxx mov re, r [re] (r) 1/1 1010 1110 0xxx xxxx mov rf, r [rf] (r) 1/1 1010 1101 0xxx xxxx mov p0, r [p0] (r) 1/1 0001 0010 i i i i i i i i mov mfp, #i [mfp] i 1/1
w742e/c811 - 56 - instruction set, continued machine code mnemonic function flag affected w/c flag & register 0101 1111 1xxx xxxx mova r, page acc, r page (page register) zf 1/1 0101 1110 1xxx xxxx mov page, r page (r) 1/1 0101 0110 1000 0i i i mov page, #i page i 1/1 1001 1101 1xxx xxxx mov r, wrp r wrp 1/1 1001 1100 1xxx xxxx mov wrp, r wrp (r) 1/1 0011 0101 1000 i i i i mov wrp, #i wrp i 1/1 0011 0101 0000 i i i i mov dbkrl, #i dbkrl i 1/1 0011 0101 0100 000 i mov dbkrh, #i dbkrh i 1/1 1001 1101 0000nnnn mov wrn,dbkrl wrn dbkrl 1/1 1001 1101 0100nnnn mov wrn,dbkrh wrn dbkrh 1/1 1001 1100 0000nnnn mov dbkrl, wrn dbkrl wrn 1/1 1001 1100 0100nnnn mov dbkrh, wrn dbkrh wrn 1/1 0011 0100 0000 0 i i i mov rompr, #i rompr i 1/1 1000 1000 0xxx xxxx mov rompr, r rompr (r) 1/1 1000 1001 0xxx xxxx mov r, rompr r (rompr) 1/1 0001 0011 1000 i 0 0 i mov mr0, #i mr0 i 1/1 0001 0011 0000 i i i i mov mr1, #i mr1 i 1/1 0101 1001 0xxx xxxx mova r, cf acc.0, r.0 cf zf 1/1 0101 1000 0xxx xxxx mov cf, r cf (r.0) cf 1/1 0100 1001 0xxx xxxx mova r, hcfl acc, r hcf.0~hcf.3 zf 1/1 0100 1001 1xxx xxxx mova r, hcfh acc, r hcf.4~hcf.7 zf 1/1 0101 0011 0000 i i i i mov pm0, #i port mode 0 i 1/1 0101 0111 0000 i i i i mov pm1, #i port mode 1 i 1/1 0101 0111 1000 i i i i mov pm2, #i port mode 2 i 1/1 0011 0111 0000 i i i i mov pm4, #i port mode 4 i 1/1 0011 0111 1000 i i i i mov pm5, #i port mode 5 i 1/1 0101 0011 1000 i i i i mov pm6, #i port mode 6 i 1/1 0100 0000 i 0 0 i i i i i clr evf, #i clear event flag if in = 1 1/1 0011 0000 0000 0000 clr evfd clear rd event flag if in = 1 1/1
w742e/c811 publication release date: april 15, 2005 - 57 - revision a2 instruction set, continued machine code mnemonic function flag affected w/c flag & register 0101 1101 0xxx xxxx mova r, evfl acc, r evf.0 - evf.3 zf 1/1 0101 1101 1xxx xxxx mova r, evfh acc, r evf.4 - evf.7 zf 1/1 0100 0001 iiii i i ii mov hef, #i set/reset hold mode release enable flag 1/1 0011 0001 0000 000 i mov hefd,#i set/reset rd hold mode release enable flag 1/1 0101 0001 iiii i i ii mov ief, #i set/reset interrupt enable flag 1/1 0100 0011 0000 i i i i mov pef, #i set/reset port enable flag 1/1 0011 0011 0000 i i 00 mov p1ef, #i set/reset p1 port enable flag 1/1 0101 0010 i i i i i i i i mov sef, #i set/reset stop mode wake-up enable flag for rc,rd port 1/1 0101 0100 0000 i i i i mov scr, #i scr i 1/1 0100 1111 0xxx xxxx mova r, psr0 acc, r port status register 0 zf 1/1 0100 1111 1xxx xxxx mova r, psr1 acc, r port status register 1 zf 1/1 0101 1111 0xxx xxxx mova r, psr2 acc, r port status register 2 zf 1/1 0100 0010 0000 0000 clr psr0 clear port status register 0 1/1 0100 0010 1000 0000 clr psr1 clear port status register 1 1/1 0100 0010 1100 0000 clr psr2 clear port status register 2 1/1 0101 0000 0100 0000 set cf set carry flag cf 1/1 0101 0000 0000 0000 clr cf clear carry flag cf 1/1 0001 0111 0000 0000 clr divr0 clear the last 4-bit of the divider 0 1/1 0101 0101 1000 0000 clr divr1 clear the last 4-bit of the divider 1 1/1 0001 0111 1000 0000 clr wdt clear watchdog timer 1/1 shift & rotate 0100 1101 0xxx xxxx shrc r acc.n, r.n (r.n+1); acc.3, r.3 0; cf r.0 zf, cf 1/1 0100 1101 1xxx xxxx rrc r acc.n, r.n (r.n+1); acc.3, r.3 cf; cf r.0 zf, cf 1/1 0100 1100 0xxx xxxx shlc r acc.n, r.n (r.n-1); acc.0, r.0 0; cf r.3 zf, cf 1/1 0100 1100 1xxx xxxx rlc r acc.n, r.n (r.n-1); acc.0, r.0 cf; cf r.3 zf, cf 1/1
w742e/c811 - 58 - instruction set, continued machine code mnemo nic function flag affected w/c lcd 1001 1000 0xxx xxxx mov lpl, r lpl (r) 1/1 1001 1000 1xxx xxxx mov lph, r lph (r) 1/1 1001 1010 0xxx xxxx mov @lp, r [(lph) 10h+(lpl)] (r) 1/1 1001 1011 0xxx xxxx mov r, @lp r [ (lph) 10h+(lpl)] 1/1 0000 0010 0000 0000 lcdon lcd on 1/1 0000 0010 1000 0000 lcdoff lcd off 1/1 0000 0011 0000 0 i i i mov lcdcc, #i lcd contrast control 1/1 serial i/o 0011 0010 0000 i i i i mov sic, #i serial interface control 1/1 1010 1111 0xxx xxxx sop r p0.1 r(high nibble),a(low nibble) serially 1/1 1001 1111 0xxx xxxx sip r r(high nibble), a(low nibble) p0.1 serially zf 1/1 dtmf 0011 0100 1000 i i i i mov dtcr, #i dtmf enable control 1/1 1001 1110 1xxx xxxx mov dtmf, r select dtmf frequency 1/1 timer 1010 1010 0xxx xxxx mov tm0l, r tm0l (r) 1/1 1010 1010 1xxx xxxx mov tm0h, r tm0h (r) 1/1 1010 1011 0xxx xxxx mov tm1l, r tm1l (r) 1/1 1010 1011 1xxx xxxx mov tm1h, r tm1h (r) 1/1 1000 1111 0xxx xxxx mov r, tm0l (r) tm0l 1/1 1000 1111 1xxx xxxx mov r, tm0h (r) tm0h 1/1 1001 1001 0xxx xxxx mov r, tm1l (r) tm1l 1/1 1001 1001 1xxx xxxx mov r, tm1h (r) tm1h 1/1 other 0000 0000 1000 0000 hold enter hold mode 1/1 0000 0000 1100 0000 stop enter stop mode 1/1 0000 0000 0000 0000 nop no operation 1/1 0101 0000 1100 0000 en int enable interrupt function 1/1 0101 0000 1000 0000 dis int disable interrupt function 1/1
w742e/c811 publication release date: april 15, 2005 - 59 - revision a2 10. package dimensions 100l qfp (14 x 20 x 2.75 mm footprint 4.8 mm) e h y a a2 seating plane l l 1 see detail f 0.08 0 7 0 0.003 2.40 1.40 19.20 1.20 18.80 1.00 18.40 0.064 0.055 0.992 0.756 0.047 0.976 0.740 0.039 0.728 0.65 20.10 14.10 0.20 0.40 2.87 20.00 14.00 2.72 19.90 13.90 0.10 0.20 2.57 0.791 0.555 0.008 0.016 0.113 0.787 0.551 0.107 0.026 0.783 0.547 0.004 0.008 0.101 symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a b c d e h d h e l y a a l 1 1 2 e 0.012 0.006 0.15 0.30 24.40 24.80 25.20 7 0.020 0.032 0.498 0.802 0.35 0.25 0.010 0.014 0.018 0.45 controlling dimension: millimeters a1 e d h d eb c 0.960
w742e/c811 - 60 - 11. revision history version date page reasons for change a1 december, 2000 - a2 april 15, 2005 - add important notice important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu chiu, taipei, 114, taiwan, r.o.c.

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